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cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 revision: v1.41 date: april 11, 2017
rev. 1.41 2 april 11, 2017 rev. 1.41 3 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom table of contents eates cpu features ......................................................................................................................... 6 peripheral features ................................................................................................................. 6 general description ........................................................................................ 7 block diagram .................................................................................................. 7 selection table ................................................................................................. 8 pin assignment ........... ..................................................................................... 8 pin descriptions .............................................................................................. 9 absolute maximum ratings .......................................................................... 10 d.c. characteristics ....................................................................................... 10 a.c. characteristics ....................................................................................... 12 a/d converter electrical characteristics ........... ......................................... 14 comparator electrical characteristics ........................................................ 14 power on reset electrical characteristics .................................................. 14 system architecture ...................................................................................... 15 clocking and pipelining ......................................................................................................... 15 program counter ................................................................................................................... 16 stack ..................................................................................................................................... 17 arithmetic and logic unit C alu ........................................................................................... 17 flash program memory ................................................................................. 18 structure ................................................................................................................................ 18 special vectors ..................................................................................................................... 18 look-up table ............. ........................................................................................................... 18 table program example ........................................................................................................ 19 in circuit programming ......................................................................................................... 20 on-chip debug support C ocds ......................................................................................... 21 ram data memory ......................................................................................... 21 structure ................................................................................................................................ 21 special function register description ........................................................ 23 indirect addressing registers C iar0, iar1 ......................................................................... 23 memory pointers C mp0, mp1 .............................................................................................. 23 bank pointer C bp ................................................................................................................. 24 accumulator C acc ............................................................................................................... 24 program counter low register C pcl .................................................................................. 24 look-up table registers C tblp, tbhp, tblh ..................................................................... 24 status register C status .................................................................................................... 25 eeprom data memory ........... ....................................................................... 27 eeprom data memory structure ........................................................................................ 27 eeprom registers ............ .................................................................................................. 27
rev. 1.41 2 april 11, 2017 rev. 1.41 3 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom reading data from the eeprom ........................................................................................ 29 writing data to the eeprom ................................................................................................ 29 write protection ..................................................................................................................... 30 eeprom interrupt ............. ................................................................................................... 30 programming considerations ............. ................................................................................... 30 programming examples ........................................................................................................ 30 oscillators .......... ............................................................................................ 32 oscillator overview ............. .................................................................................................. 32 system clock confgurations ................................................................................................ 32 external crystal/ceramic oscillator C hxt ........................................................................... 33 internal rc oscillator C hirc ............. .................................................................................. 34 internal 32khz oscillator C lirc ........................................................................................... 34 supplementary oscillator ...................................................................................................... 34 operating modes and system clocks ......................................................... 35 system clocks ...................................................................................................................... 35 system operation modes ...................................................................................................... 37 control register .................................................................................................................... 38 fast wake-up ........................................................................................................................ 39 operating mode switching ................................................................................................... 40 standby current considerations ........................................................................................... 44 wake-up ................................................................................................................................ 44 programming considerations ............. ................................................................................... 45 watchdog timer ........... .................................................................................. 46 watchdog timer clock source .............................................................................................. 46 watchdog timer control register ............. ............................................................................ 46 watchdog timer operation ................................................................................................... 47 reset and initialisation .................................................................................. 48 reset functions ............. ....................................................................................................... 48 reset initial conditions ......................................................................................................... 51 input/output ports ......................................................................................... 53 pull-high resistors ................................................................................................................ 53 port a wake-up ............. ........................................................................................................ 54 i/o port control registers ..................................................................................................... 54 special pin control ................................................................................................................ 55 pin-remapping functions ...................................................................................................... 55 i/o pin structures .................................................................................................................. 57 programming considerations ............. ................................................................................... 58 timer modules C tm .......... ............................................................................ 59 introduction ........................................................................................................................... 59 tm operation ............. ........................................................................................................... 59 tm clock source ............. ...................................................................................................... 60 tm interrupts ......................................................................................................................... 60 tm external pins ................................................................................................................... 60
rev. 1.41 4 april 11, 2017 rev. 1.41 5 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom tm input/output pin control register ................................................................................... 61 programming considerations ............. ................................................................................... 63 compact type tm C ctm .............................................................................. 64 compact tm operation ......................................................................................................... 64 compact type tm register description ................................................................................ 65 compact type tm operating modes .................................................................................... 70 standard type tm C stm .......... .................................................................... 76 standard tm operation ............. ............................................................................................ 76 standard type tm register description ............................................................................... 77 standard type tm operating modes .................................................................................... 81 analog to digital converter .......... ................................................................ 91 a/d overview ............. ........................................................................................................... 91 a/d converter register description ...................................................................................... 91 a/d converter data registers C adrl, adrh ..................................................................... 92 a/d converter control registers C adcr0, adcr1, acer ................................................. 92 a/d operation ....................................................................................................................... 95 a/d input pins ............. .......................................................................................................... 96 summary of a/d conversion steps ............. .......................................................................... 97 programming considerations ............. ................................................................................... 98 a/d transfer function ............. .............................................................................................. 98 a/d programming examples ................................................................................................. 99 comparator .......... ........................................................................................ 101 comparator operation ........................................................................................................ 101 comparator interrupt ........................................................................................................... 102 programming considerations ............. ................................................................................. 102 interrupts ...................................................................................................... 103 interrupt registers ............................................................................................................... 103 interrupt operation .............................................................................................................. 107 external interrupt ............. .................................................................................................... 109 comparator interrupt ........................................................................................................... 109 multi-function interrupt ........................................................................................................ 109 a/d converter interrupt ........................................................................................................ 110 time base interrupts ............................................................................................................ 110 eeprom interrupt ............. .................................................................................................. 112 tm interrupts ........................................................................................................................ 112 interrupt wake-up function .................................................................................................. 112 programming considerations ............. .................................................................................. 113 confguration options .................................................................................. 114 application circuits ........... ........................................................................... 114 instruction set ............................................................................................... 115 instruction ............. ................................................................................................................ 115 instruction timing ................................................................................................................. 115 moving and transferring data .............................................................................................. 115
rev. 1.41 4 april 11, 2017 rev. 1.41 5 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom arithmetic operations ........................................................................................................... 115 logical and rotate operations ............. ................................................................................ 116 branches and control transfer ............................................................................................ 116 bit operations ...................................................................................................................... 116 table read operations ........................................................................................................ 116 other operations ............. ..................................................................................................... 116 instruction set summary .......... ................................................................... 117 table conventions ................................................................................................................ 117 instruction defnition .................................................................................... 119 package information ................................................................................... 128 8-pin dip (300mil) outline dimensions ............................................................................... 129 8-pin sop (150mil) outline dimensions ............................................................................. 130 10-pin msop outline dimensions ...................................................................................... 131 16-pin nsop (150mil) outline dimensions ......................................................................... 132
rev. 1.41 6 april 11, 2017 rev. 1.41 7 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom features cpu features ? operating v oltage f sys =8mhz: 2.2v~5.5v f sys =12mhz: 2.7v~5.5v f sys =16mhz: 3.3v~5.5v f sys =20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? three oscillators external crystal -- hxt internal rc -- hirc internal 32khz -- lirc ? fully intergrated internal 4 mhz, 8mhz, 12 mhz oscillator requires no external components ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 8 -level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 2k16 ~ 4k16 ? ram data memory: 1608 ~ 2568 ? true eeprom memory: 5128 ~ 10248 ? watchdog t imer function ? 8 bidirectional i/o lines ? one pin-shared external interrupt ? multiple t imer module for time measure, compare match output, pwm output function or single pulse output function ? dual t ime-base functions for generation of fxed time interrupt signals ? 5-channel 12-bit resolution a/d converter ? single comparator function ? low voltage reset function ? package t ypes: 8-pin dip/sop and 10-pin msop ? flash program memory can be re-programmed up to 100,000 times ? flash program memory data retention > 10 years ? true eeprom data memory can be re-programmed up to 1,000,000 times ? true eeprom data memory data retention > 10 years
rev. 1.41 6 april 11, 2017 rev. 1.41 7 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom general description these devices are flash memory type 8-bit high performance risc architecture microcontrollers. offering use rs t he c onvenience of fl ash me mory m ulti-programming fe atures, t hese de vices a lso include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-cha nnel 12-bit a/d converter and a comparator functions. multiple and extremely flexible t imer modules provide timing, pulse generation and pwm generation functions. protective features such as an internal w atchdog t imer, low v oltage reset coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt , hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate a nd swi tch d ynamically b etween a r ange o f o perating m odes u sing d ifferent c lock so urces gives users the ability to optimise microcontroller operation and minimize power consumption. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vices wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. block diagram 8-bit risc mcu core 16-bit stm1 flash program memory eeprom data memory flash/eeprom programming circuitry ram data memory time bases watchdo g timer interrupt controller reset circuit external oscillator low voltage reset 10-bit ctm2 i/o 12-bit a/d converter comparator internal rc oscillators
rev. 1.41 8 april 11, 2017 rev. 1.41 9 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom selection table most fe atures a re c ommon t o t hese de vices, t he m ain fe atures di stinguishing t hem a re me mory capacity. the following table summarises the main features of each device. part no. v dd rom ram eeprom i/o ext. int. a/d timer module time base stack package HT66F007 2.2v~ 5.5v 2k16 1608 5128 8 1 12-bit5 10-bit ctm2 16-bit stm1 2 8 8dip/sop 10msop ht66f008 2.2v~ 5.5v 4k16 2568 10248 8 1 12-bit5 10-bit ctm2 16-bit stm1 2 8 8dip/sop 10msop pin assignment

note: 1. bracketed pin names indicate non-default pinout remapping locations. 2. if the pin-shared pin functions have multiple outputs simultaneously , its pin names at the right side of the / sign can be used for higher priority. 3. a vdd&vdd m eans t he vdd a nd a vdd a re t he d ouble bo nding. vss& avss m eans t he vss a nd avss are the double bonding.
rev. 1.41 8 april 11, 2017 rev. 1.41 9 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom pin descriptions with the exception of the power pins, all pins on these devices can be referenced by their port name, e.g. p a0, p a1 etc, which refer to the digital i/o function of the pins. however these port pins are also shared with other function such as the analog to digital converter , t imer module pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. as the pin description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. pin name function op i/t o/t pin-shared mapping pa0~pa7 general purpose i/o port a papu pawu st cmos an0~an4 a/d converter input 0~4 acer an pa0~pa3, pa5 vref a/d converter reference voltage input adcr1 an pa1 int external interrupt prm st pa5 or pa2 or pa3 or pa7 tck0 tm0 input prm st pa7 or pa6 tck1 tm1 input prm st pa2 or pa4 or pa7 tp0_0 tm0 i/o prm st cmos pa0 tp0_1 tm0 i/o prm st cmos pa5 or pa1 tp1_0 tm1 i/o prm st cmos pa6 or pa7 tp1_1 tm1 i/o prm st cmos pa4 tp2_0 tm2 i/o prm st cmos pa2 osc1 hxt pin co hxt pa6 osc2 hxt pin co hxt pa5 cp comparator positive input cpc an pa0 cn comparator negative input an pa1 cx comparator output cmos pa2 icpck icp clock input st pa1 icpda icp data input/output st cmos pa0 vdd positive power supply* pwr avdd a/d converter power supply* pwr vss negative power supply, ground** pwr avss a/d converter ground** pwr the following pins are only for the ht66v007/ht66v008 ocdsck on-chip debug support clock pin st ocdsda on-chip debug support data/address pin st cmos legend: : i/t: input type o/t: output type op: optional by confguration option (co) or register option pwr: power co: confguration option st: schmitt t rigger input cmos: cmos output an: analog signal hxt: high frequency ctystal oscillator *: vdd is the device power supply while a vdd is the adc power supply . the a vdd pin is bonded together internally with vdd. **: vss is the device ground pin while a vss is the adc ground pin. the a vss pin is bonded together internally with vss.
rev. 1.41 10 april 11, 2017 rev. 1.41 11 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom absolute maximum ratings supply v oltage .............. .................................................................................. v ss ?0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss ? 0.3v to v dd +0.3v storage t emperature ............... ..................................................................................... -50? c to 125?c operating t emperature .............. .................................................................................... -40? c to 85 ?c i oh t otal .............. .................................................................................................................... -100ma i ol t otal .............. ..................................................................................................................... 100ma total power dissipation .............. .......................................................................................... 500mw note: t hese a re st ress ra tings onl y. st resses e xceeding t he ra nge spe cified und er "absol ute ma ximum ratings" m ay c ause su bstantial d amage t o t hese d evices. fu nctional o peration o f t hese d evices a t other c onditions be yond t hose l isted i n t he spe cifcation i s no t i mplied a nd pr olonged e xposure t o extreme conditions may affect devices reliability. d.c. characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 operating voltage (hxt) f sys =8mhz 2.2 5.5 v f sys =12mhz 2.7 5.5 v f sys =16mhz 3.3 5.5 v f sys =20mhz 4.5 5.5 v v dd2 operating voltage (hirc) f sys =4mhz 2.2 5.5 v f sys =8mhz 2.2 5.5 v f sys =12mhz 2.7 5.5 v i dd1 operating current, normal mode, f sys =f h (hxt) 3v no load, f h =4 mhz, adc off, wdt enable 0.6 0.9 ma 5v 1.8 2.7 ma 3v no load, f h =8 mhz, adc off, wdt enable 1.1 1.7 ma 5v 2.9 4.4 ma 3v no load, f h =12 mhz, adc off, wdt enable 1.6 2.5 ma 5v 4.1 6.2 ma 3.3v no load, f h = 16 mhz, adc off, wdt enable 2.0 3.0 ma 5v 5.2 7.8 ma 5v no load, f h =20mhz, adc off, wdt enable 6.4 9.6 ma i dd2 operating current, normal mode, f sys =f h (hirc) 3v no load, f h =4 mhz, adc off, wdt enable 0.6 0.9 ma 5v 1.8 2.7 ma 3v no load, f h =8 mhz, adc off, wdt enable 1.1 1.7 ma 5v 2.9 4.4 ma 3v no load, f h =12 mhz, adc off, wdt enable 1.6 2.5 ma 5v 4.1 6.2 ma
rev. 1.41 10 april 11, 2017 rev. 1.41 11 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i dd3 operating current, normal mode, f h =12mhz (hirc) 3v no load, f sys =f h /2, adc off, wdt enable 1.7 2.4 ma 5v 2.6 4.4 ma 3v no load, f sys =f h /4, adc off, wdt enable 1.6 2.4 ma 5v 2.4 4.0 ma 3v no load, f sys =f h /8, adc off, wdt enable 1.5 2.2 ma 5v 2.2 3.6 ma 3v no load, f sys =f h /16, adc off, wdt enable 1.4 2.0 ma 5v 2.0 3.2 ma 3v no load, f sys =f h /32, adc off, wdt enable 1.3 1.8 ma 5v 1.8 2.8 ma 3v no load, f sys =f h /64, adc off, wdt enable 1.2 1.6 ma 5v 1.6 2.4 ma i dd4 operating current, normal mode, f h =12mhz (hxt) 3v no load, f sys =f h /2, adc off, wdt enable 0.90 1.50 ma 5v 2.50 3.75 ma 3v no load, f sys =f h /4, adc off, wdt enable 0.7 1.0 ma 5v 2.0 3.0 ma 3v no load, f sys =f h /8, adc off, wdt enable 0.6 0.9 ma 5v 1.6 2.4 ma 3v no load, f sys =f h /16, adc off, wdt enable 0.50 0.75 ma 5v 1.50 2.25 ma 3v no load, f sys =f h /32, adc off, wdt enable 0.49 0.74 ma 5v 1.45 2.18 ma 3v no load, f sys =f h /64, adc off, wdt enable 0.47 0.71 ma 5v 1.40 2.10 ma i dd5 operating current, slow mode, f sys =f l =lirc, f sub =lirc 3v no load, f sys =lirc, adc off, wdt enable , lvr disable 10 20 a 5v 30 50 a i dd5a operating current, slow mode, f sys =f l =lirc, f sub =lirc 3v no load, f sys =lirc, adc off, wdt enable , lvr enable 40 60 a 5v 90 135 a i idle01 idle0 mode standby current (lirc on) 3v no load, adc off, wdt enable 1.3 3.0 a 5v 2.2 5.0 a i idle11 idle1 mode standby current (hxt) 3v no load, adc off, wdt enable, f sys =4mhz on 0.4 0.8 ma 5v 0.8 1.6 ma i idle11 a idle1 mode standby current (hirc) 3v no load, adc off, wdt enable, f sys =4mhz on 0.4 0.8 ma 5v 0.8 1.6 ma i idle12 idle1 mode standby current (hxt) 3v no load, adc off, wdt enable, f sys =8mhz on 0.5 1.0 ma 5v 1.0 2.0 ma i idle12a idle1 mode standby current (hirc) 3v no load, adc off, wdt enable, f sys =8mhz on 0.8 1.6 ma 5v 1.0 2.0 ma i idle13 idle1 mode standby current (hxt) 3v no load, adc off, wdt enable, f sys = 12mhz on 0.6 1.2 ma 5v 1.2 2.4 ma i idle13a idle1 mode standby current (hirc) 3v no load, adc off, wdt enable, f sys =12mhz on 0.6 1.2 ma 5v 1.2 2.4 ma i idle14 idle1 mode standby current (hxt) 3.3v no load, adc off, wdt enable, f sys =16mhz on 1.0 2.0 ma 5v 2.0 4.0 ma i idle15 idle1 mode standby current (hxt) 5v no load, adc off, wdt enable, f sys =20mhz on 2.5 5.0 ma
rev. 1.41 12 april 11, 2017 rev. 1.41 13 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions i sleep0 sleep0 mode standby current (lirc off ) 3v no load, adc off, wdt disable, lvr disable 0.2 0.8 a 5v 0.5 1.0 a i sleep1 sleep1 mode standby current (lirc on) 3v no load, adc off, wdt enable, lvr disable 1.3 5.0 a 5v 2.2 10 a v il1 input low voltage for i/o ports or input pins 5v 0 1.5 v 0 0.2v dd v v ih1 input high voltage for i/o ports or input pins 5v 3.5 5.0 v 0.8v dd v dd v v il2 ttl input low voltage for pa2, pa5, pa6 and pa7 5v 5v10% 0 0.8 v v ih2 ttl input high voltage for pa2, pa5, pa6 and pa7 5v 5v10% 2.0 v dd v v lvr low voltage reset voltage lvr enable, 2.1v option -5% typ. 2.1 +5% typ. v lvr enable, 2.55v option 2.55 v lvr enable, 3.15v option 3.15 v lvr enable, 3.8v option 3.8 v i lvr additional power consumption if lvr is used 3v lvr disable lvr enable 30 45 a 5v 60 90 a i ol i/o port sink current 3v v ol =0.1v dd 8 16 ma 5v v ol =0.1v dd 16 32 ma i oh i/o port source current 3v v oh =0.9v dd -3.75 -7.5 ma 5v v oh =0.9v dd -7.5 -15 ma r ph pull-high resistance for i/o ports 3v 20 60 100 k 5v 10 30 50 k i ocds operating current, normal mode, f sys =f h (hirc) (for ocds ev testing, connect to an e-link) 3v no load, f h =4 mhz, adc off, wdt enable 0.7 1.0 ma a.c. characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu operating clock 2.2v~5.5v dc 8 mhz 2.7v~5.5v dc 12 mhz 3.3v~5.5v dc 16 mhz 4.5v~5.5v dc 20 mhz f sys system clock (hxt) 2.2v~5.5v 0.4 8 mhz 2.7v~5.5v 0.4 12 mhz 3.3v~5.5v 0.4 16 mhz 4.5v~5.5v 0.4 20 mhz
rev. 1.41 12 april 11, 2017 rev. 1.41 13 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom symbol parameter test conditions min. typ. max. unit v dd conditions f hirc system clock (hirc) 3v/5v ta=25c -2% 4 +2% mhz 3v/5v -2% 8 +2% mhz 3v/5v -2% 12 +2% mhz 3v/5v ta=0c~ 70c -4% 4 +3% mhz 3v/5v -4% 8 +3% mhz 3v/5v -4% 12 +3% mhz 3v/5v ta=-40c~85c -7% 4 +7% mhz 3v/5v -7% 8 +7% mhz 3v/5v -7% 12 +7% mhz 2.2v~4.0v ta=0c~ 70c -9% 4 +6% mhz 3.0v~5.5v -5% 4 +12% mhz 2.2v~4.0v ta=0c~ 70c -9% 8 +5% mhz 3.0v~5.5v -5% 8 +11 % mhz 2.7v~4.0v ta=0c~ 70c -10% 12 +10% mhz 3.0v~5.5v ta=0c~ 70c -10% 12 +10% mhz 2.2v~4.0v ta=-40c~85c -12% 4 +6% mhz 3.0v~5.5v ta=-40c~85c -8% 4 +12% mhz 2.2v~4.0v ta=-40c~85c -12% 8 +6% mhz 3.0v~5.5v ta=-40c~85c -8% 8 +12% mhz 2.7v~4.0v ta=-40c~85c -13% 12 +13% mhz 3.0v~5.5v ta=-40c~85c -13% 12 +13% mhz 2.2v~5.5v ta=-40c ~85c -15% 4 +15% mhz 2.2v~5.5v -15% 8 +15% mhz 2.7v~5.5v -15% 12 +15% mhz f lirc system clock (lirc) 5v ta=25c -10 % 32 +10% khz 2.2v~5.5v ta=-40c ~85c -50% 32 +60% khz t timer tckn input pulse width 0.3 s t int interrupt pulse width 10 s t lvr low voltage width to reset 120 240 480 s t sreset software reset width to reset 45 90 120 s t eerd eeprom read time 2 4 t sys t eewr eeprom write time 2 4 ms t sst system start-up timer period (wake-up from halt) f sys = hxt 1024 t sys f sys =hirc 15~16 t sys f sys =lirc 1~2 t sys t rstd system reset delay time (power on reset , lvr reset, lvr s/w reset(lvrc), wdt s/w reset(wdtc) ) 25 50 100 ms system reset delay time ( wdt normal reset) 8.3 16.7 33.3 ms 1rwh w sys i sys dd h dffudf i h hudo , foodu iuhthf d hfso fdsdfu o h fhfh hhh d 66 d ofdh d foh h hyfh d soh
rev. 1.41 14 april 11, 2017 rev. 1.41 15 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom a/d converter electrical characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d converter operating voltage 2.7 5.5 v v adi a/d converter input voltage 0 v ref v v ref a/d converter reference voltage 2 a v dd v v bg reference voltage with buffer voltage -3% 1.25 +3% v dnl differential non-linearity 2.7v v ref =av dd =v dd t adck =0.5s -2 +2 lsb 3v 5v inl integral non-linearity 2.7v v ref =av dd =v dd t adck =0.5s -4 +4 lsb 3v 5v i adc additional power consumption if a/d converter is used 3v no load (t adck =0.5s ) 0.9 1.35 ma 5v no load (t adck =0.5s ) 1.2 1.8 ma i bg additional power consumption if v bg reference with buffer is used 200 300 a t adck a/d converter clock period 0.5 10 s t adc a/d conversion time (include sample and hold time) 12-bit adc 16 t adck t ads a/d converter sampling time 4 t adck t on2st a/d converter on-to-start time 2 s t bgs v bg turn on stable time 200 s comparator electrical characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions comparator operating voltage 2.2 5.5 v i cm comparator operating current 3v 50 75 a 5v 85 130 a v cmpos comparator input offset voltage 5v -10 +10 mv v hys hysteresis width 5v 20 40 60 mv v cm comparator common mode voltage range v ss v dd -1.4 v a ol comparator open loop gain 60 80 db t pd comparator response time with 100mv overdrive (note) 300 600 ns 1rwh 0hdvxuhg zlwk frpsdudwru rh lsxw sl dw 9 &0 9 dd oh h hu s s ud iu ss u iu dd power on reset electrical characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start voltage to ensure power-on reset 100 mv rr vdd v dd rising rate to ensure power-on reset 0.035 v/ms t por minimum time for v dd stays at v por to ensure power-on reset 1 ms
rev. 1.41 14 april 11, 2017 rev. 1.41 15 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and fexibility . this makes the devices suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt , hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? ? ? ? system clock and pipelining
rev. 1.41 16 april 11, 2017 rev. 1.41 17 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications.
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. only the lower 8 bits, known as the program counter low register , are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register HT66F007 pc10~pc8 pcl7~pcl0 ht66f008 pc11~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.41 16 april 11, 2017 rev. 1.41 17 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost.
arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation: rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement: inca, inc, deca, dec ? branch decision: jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
rev. 1.41 18 april 11, 2017 rev. 1.41 19 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom flash program memory the program memory is the location where the user code or program is stored. for these devices the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, these flash devices of fer users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the program memory has a capaci ty of 2k16 to 4k16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. t able data, which c an b e se tup i n a ny l ocation wi thin t he pro gram me mory, i s a ddressed b y a se parate t able pointer register. device capacity HT66F007 2k16 ht66f008 4k16 000h 004h 024h 7ffh reset interrupt vector 16 bits reset 16 bits fffh HT66F007 ht66f008 interrupt vector program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd [m] or t abrdl [m] instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0.
rev. 1.41 18 april 11, 2017 rev. 1.41 19 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom the accompanying diagram illustrates the addressing data fow of the look-up table. last page or tbhp register address tblp register data 16 bits program memory register tblh user selected register high byte low byte table program example the f ollowing e xample sh ows h ow t he t able p ointer a nd t able d ata i s d efned a nd r etrieved f rom t he microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k words program memory of the HT66F007. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the t abrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or present page mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 705h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.41 20 april 11, 2017 rev. 1.41 21 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek write pins mcu programming pins function icpda pa0 programming serial data/address icpck pa1 programming serial clock vdd vdd power supply vss vss ground the program memory and eeprom data memory can both be programmed serially in-circuit using this 4-wi re inte rface. dat a is downloaded and upl oaded serial ly on a single pin wit h an additi onal line for the clock. t wo additional lines are required for the power supply and ground. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature.
note: * may be resistor or capacitor . the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf.
rev. 1.41 20 april 11, 2017 rev. 1.41 21 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom on-chip debug support C ocds there a re t wo e v chips named ht 66v007 a nd ht 66v008 whi ch a re u sed t o e mulate t he ht 66f007 and ht 66f008 re pectively. t hese e v c hip de vices a lso provi de a n on-chip de bug func tion t o debug the device during the development process. the ev chip and the actual mcu devices are almost functionally compatible except for the on-chip debug function. users can use the ev chip device to emulate the real chip device behavior by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/ output pin while the ocdsck pin is the ocds clock input pin. when users use the ev chip for debugging, ot her func tions whi ch a re sha red wi th t he ocdsda a nd ocdsck pi ns i n t he a ctual mcu device will have no ef fect in the ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for a more detailed ocds description, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins pin description ocdsda ocdsda on-chip debug support data/address input/output ocdsck ocdsck on-chip debug support clock input vdd vdd power supply gnd vss ground ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. here are located registers which are necessary for correct operation of the devices. many of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the devices is the address 00h.
rev. 1.41 22 april 11, 2017 rev. 1.41 23 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom device ram address HT66F007 special purpose bank0: 00h~3fh bank1: 00h~40h (eec in 40h) general purpose: 1608 bank0: 40h~dfh ht66f008 special purpose bank0: 00h~40h bank1: 00h~40h (eec in 40h) general purpose: 2568 bank0: 80h~ffh bank1: 80h~ffh

? ?
? ?

?? ?? - ?? ? ? special purpose data memory structure
rev. 1.41 22 april 11, 2017 rev. 1.41 23 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operatio n to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according t o bp register. direct ad dressing c an only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org 00h start: m ov a,04h ; setup size of block m ov block,a mov a ,offset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0,a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.41 24 april 11, 2017 rev. 1.41 25 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom bank pointer C bp for these devices, the data memory is di vided into two ba nks, ba nk0 and ba nk1. selecting the required data memory area is achieved using the bank pointer . bit 0 of the bank pointer is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wd t time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by the bank selection, which means that the special function regi sters ca n be ac cessed from wi thin any bank. di rectly addressi ng the da ta me mory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from bank1 must be implemented using indirect addressing. bp register bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location.
rev. 1.41 24 april 11, 2017 rev. 1.41 25 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also af fected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power -up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cle ared by a system power -up or executing the clr wdt or hal t instruction. to is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
rev. 1.41 26 april 11, 2017 rev. 1.41 27 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 "" unknown bit 7~6 unimplemented, read as 0 bit 5 to : w atchdog t ime-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.41 26 april 11, 2017 rev. 1.41 27 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom eeprom data memory one of the special features in the devices is their internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory , with data retention even when its power supply is removed. by incorporating this kind of data mem ory, a whol e new host of appl ication possibi lities are ma de avail able to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the e eprom da ta me mory c apacity v aries f rom 5 128 t o 1 0248 b its. un like t he pr ogram memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address HT66F007 5128 000h~1ffh ht66f008 10248 000h~3ffh eeprom registers four re gisters c ontrol t he ove rall ope ration of t he i nternal e eprom da ta me mory. t hese a re t he address registers, eea and eeah, the data register , eed and a single control register , eec. as all the eea, eeah and eed registers are located in bank 0, they can be directly accessed in the same way a s a ny o ther sp ecial fu nction r egister. t he e ec r egister h owever, b eing l ocated i n b ank1, cannot be directly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp , set to the value, 01h, before any operat ions on the eec register are executed. register name bit 7 6 5 4 3 2 1 0 eea d7 d6 d5 d4 d3 d2 d1 d0 eeah d8 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd eeprom control registers list C HT66F007 register name bit 7 6 5 4 3 2 1 0 eea d7 d6 d5 d4 d3 d2 d1 d0 eeah d9 d8 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd eeprom control registers list C ht66f008
rev. 1.41 28 april 11, 2017 rev. 1.41 29 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom eea register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 data eeprom address data eeprom address bit 7~bit 0 eeah register C HT66F007 bit 7 6 5 4 3 2 1 0 name d8 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 data eeprom address data eeprom address bit 8 eeah register C ht66f008 bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 data eeprom address data eeprom address bit 9 ~ bit 8 eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 data eeprom data data eeprom data bit 7~bit 0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations.
rev. 1.41 28 april 11, 2017 rev. 1.41 29 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom bit 2 wr : eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea and eeah registers. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates , the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom the eeprom address of the data to be written must then be placed in the eea and eeah registers and the data place d in the eed register . t o write data to the eeprom, the write enable bit, wren, in the eec register must first be set high to enable the write function. after this, the wr bit in the e ec r egister m ust be i mmediately se t hi gh t o i nitiate a wri te c ycle. t hese t wo i nstructions must be executed consecutively . the global interrupt bit emi should also first be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended.
rev. 1.41 30 april 11, 2017 rev. 1.41 31 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom write protection protection against inadvertent w rite operation is provided in several ways . after the devices are powered-on the w rite enable bit in the control register will be cleared preventing any write operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must first be enabled by setting the dee bit in the relevant interrupt register . when an eeprom write cycle ends, the def request fag will be set. if the global and eeprom interrupts are enabled and the stack is not full, a jump to the associated interrupt vector will take place. when the interrupt is serviced the eeprom interrupt fag will be automatica lly reset. more details can be obtained in the interrupt section. programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1where the eeprom control regis ter exis t. a lthough certainly not neces sary, cons ideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the devices should not enter the idle or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming examples reading data from the eeprom C polling method mov a , ee prom_adres_h ; u ser d efned h igh-byte ad dress mov e eah, a mov a , ee prom_adres_l ; u ser d efned l ow-byte ad dress mov e ea, a mov a , 0 40h ; s etup m emory p ointer m p1 mov mp1, a ; mp1 p oints t o e ec r egister mov a , 0 1h ; s etup b ank p ointer mov b p, a set i ar1.1 ; s et r den b it, e nable r ead o perations set i ar1.0 ; s tart r ead c ycle - s et r d b it back: sz i ar1.0 ; c heck f or r ead c ycle e nd jmp b ack clr i ar1 ; d isable e eprom r ead/write clr bp mov a , ee d ; m ove re ad d ata t o re gister mov r ead_data, a
rev. 1.41 30 april 11, 2017 rev. 1.41 31 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom writing data to the eeprom C polling method mov a , ee prom_adres_h ; u ser d efned h igh-byte ad dress mov e eah, a mov a , ee prom_adres_l ; u ser d efned l ow-byte ad dress mov e ea, a mov a , e eprom_data ; u ser d efned da ta mov e ed, a mov a , 0 40h ; s etup m emory p ointer m p1 mov mp1, a ; mp1 p oints t o e ec r egister mov a , 0 1h ; s etup b ank p ointer mov b p, a clr e mi set i ar1.3 ; s et w ren b it, e nable w rite o perations set i ar1.2 ; s tart w rite c ycle - s et w r b it set e mi back: sz i ar1.2 ; c heck f or w rite c ycle e nd jmp b ack clr i ar1 ; d isable e eprom r ead/write clr bp
rev. 1.41 32 april 11, 2017 rev. 1.41 33 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom oscillators various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for the w atchdog t imer and t ime base interrupts. an external oscillator requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided t o f orm a wi de r ange o f b oth f ast a nd sl ow sy stem o scillators. t he h igh sp eed o scillator options are selected through the configuration options. the higher frequency oscillators provide higher perform ance but ca rry wi th i t t he disadva ntage of higher power requirem ents, whil e t he opposite is of course true for the lower frequency oscillators. w ith the capability of dynamically switching between fast and slow system clock, the devices have the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins external crystal hxt 400khz~20mhz osc1/osc2 internal high speed rc hirc 4, 8, 12mhz internal low speed rc lirc 32khz oscillator types system clock confgurations there are three methods of generating the system clock, two high speed oscillators and a low speed oscillator. the high speed oscillators are the external crystal/ceramic oscillator and the internal 4mhz, 8mhz, 12mhz rc oscillator . the low speed oscillator is the internal 32khz rc oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2~cks0 bits in the smod register and as the system clock can be dynamically selected. the actua l source clock used for the high speed oscillator is chosen via confguration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2~cks0 bi ts i n t he smod re gister. not e t hat t wo osc illator sel ections m ust be m ade na mely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator . the osc1 and osc2 pins are used to connect the external components for the external crystal.
rev. 1.41 32 april 11, 2017 rev. 1.41 33 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom

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?? ? ? system clock confgurations external crystal/ceramic oscillator C hxt the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the mcuas possible.
? ? ?? crystal/resonator oscillator C hxt
rev. 1.41 34 april 11, 2017 rev. 1.41 35 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom crystal oscillator c1 and c2 values crystal frequency c1 c2 12mhz 0pf 0pf 8mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf note: c1 and c2 values are for guidance only. crystal recommended capacitor values internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the i nternal r c o scillator h as t hree fx ed f requencies o f e ither 4 mhz, 8 mhz o r 1 2mhz. de vice trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the os cillation frequency are minimis ed. a s a res ult, at a pow er s upply of 3v or 5v and at temperature of 25c, the three fxed oscillation frequencies of the hirc will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pa6 and pa5 are free for use as normal i/o pins. internal 32khz oscillator C lirc the internal 32khz system oscillator is the low frequency oscillator . it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a tempe rature of 25?c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. supplementary oscillator the low speed os cillator, in addition to providing a system clock source is also used to provide a c lock so urce t o t wo o ther d evice f unctions. t hese a re t he w atchdog t imer a nd t he t ime b ase interrupts.
rev. 1.41 34 april 11, 2017 rev. 1.41 35 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the devices have many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the m ain syst em c lock, c an c ome fro m e ither a hi gh fre quency, f h , or a l ow fre quency, f l , a nd i s selected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock can be sourced from either an hxt or hirc oscillator , selected via a confguration option. the low speed system clock source can be sourced from the internal clock f l . if f l is selected then it can be sourced from the lirc oscillator . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the t ime base clock, f tbc . each of these internal clocks is sourced by the lirc oscillator . the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times.
rev. 1.41 36 april 11, 2017 rev. 1.41 37 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom

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??? ? ? ? ? ? ? ? ?? - ? system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillator will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use.
rev. 1.41 36 april 11, 2017 rev. 1.41 37 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 modes are used when the microcontroller cpu is switched of f to conserve power. operating mode description cpu f sys f lirc /f sub f tbc normal mode on f h ~f h /64 on on slow mode on f l on on ilde0 mode off off on on idle1 mode off on on on sleep0 mode off off off off sleep1 mode off off on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, hxt or hirc. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register . although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from the low speed oscil lator lirc . running the micro controller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f lirc clock will be stopped too, and the w atchdog t imer function is disabled. sleep1 mode the sleep mode is entered when an hal t instruction is executed and when the idlen bit in the smod register is low . in the sleep 1 mode the cpu will be stopped. however the f lirc clocks will continue to operate if the w atchdog t imer function is enabled . idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod regi ster i s high and t he fsyson bit i n t he ctrl regi ster i s l ow. in t he idle 0 mode t he system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer and tms. in the idle0 mode, the system oscillator will be stopped.
rev. 1.41 38 april 11, 2017 rev. 1.41 39 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the ctrl register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer and tms. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the watchdog timer clock, f lirc , will be on. control register a single register, smod, is used for overall control of the internal clocks within the devices. smod register bit 7 6 5 4 3 2 1 0 name cks2 cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 : the system clock selection when hlclk is 0 000: f l (f lirc ) 001: f l (f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 : fast w ake-up control (only for hxt) 0: disable 1: enable this i s t he fa st w ake-up c ontrol b it wh ich d etermines i f t he f sub c lock so urce i s initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temp orary system clock to provide a faster wake up time as the f sub clock is available. bit 3 : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode, but after a wake-up has occurred the fag will change to a high level after 1~2 cycles if the lirc oscillator is used. bit 2 : high speed system oscillator ready fag 0: not ready 1: ready this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this fag will always be read as 1 by the application program after device power -on. the fag will be low when in the sleep or idle0 mode, but after power on reset or a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the hirc oscillator is used.
rev. 1.41 38 april 11, 2017 rev. 1.41 39 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk : system clock selection 0: f h /2~f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2~f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2~f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. to minimise power consumption the devices can enter the sleep or idle0 mode, where the system clock source to the devices will be stopped. however when the devices are woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation t o re sume. t o e nsure t he de vices a re up a nd run ning a s fa st a s possi ble a fa st w ake-up function is provi ded, whi ch al lows f sub , namely the lirc osci llator, to ac t as a te mporary cl ock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast w ake-up function is f sub , the fast w ake-up function is only available in the sleep1 and idle0 modes. when the devices are woken up from the sleep0 mode, the fast w ake-up function has no ef fect because the f sub clock is stopped. the fast w ake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscil lator is sel ected as the normal mode syste m cl ock, and if the fa st w ake-up function is enabled, then it will take one to two t sub clock cycles of the lirc oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hx t clock cycles have elapsed, at which point the ht o fag will switch high and the system will switch over to operating from the hxt oscillator. if the hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock c ycles of t he hirc or 1~2 c ycles of t he l irc t o wa ke up t he syst em from t he sl eep or idle0 mode. the fast w ake-up bit, fsten will have no effect in these cases. hxt 0 1024 hxt cycles 1024 hxt cycles 1~2 hxt cycles 1 1024 hxt cycles 1~2 f sub cycles (system runs with f sub frst for 1024 hxt cycles and then switches over to run with the hxt clock) 1~2 hxt cycles hirc 15~16 hirc cycles 15~16 hirc cycles 1~2 hirc cycles lirc 1~2 lirc cycles 1~2 lirc cycles 1~2 lirc cycles note that if the w atchdog t imer is disabled, which means that the lirc is of f, then there will be no fast w ake-up function available when the devices wake-up from the sleep0 mode.
rev. 1.41 40 april 11, 2017 rev. 1.41 41 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom
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operating mode switching the d evices c an swi tch b etween o perating m odes d ynamically a llowing t he u ser t o se lect t he b est performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction . when a hal t instructio n is executed, whether the devices enter the idle mode or the sleep mode is determined by the condit ion of the idl en bit in the smod regi ster and fsyson in the ctrl register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tms. the accompanying flowchart shows what happens when the devices move between the various operating modes.
rev. 1.41 40 april 11, 2017 rev. 1.41 41 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syst em c lock c an swi tch t o run i n t he sl ow mode by se tting t he hlclk bit to 0 and setting the cks2~cks0 bits to 000 or 001 in the smod register .this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.
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rev. 1.41 42 april 11, 2017 rev. 1.41 43 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom slow mode to normal mode switching in slow mode the system uses lirc low speed system oscillator . t o switch back to the normal mode, w here the high s peed s ystem os cillator is us ed, the h lclk bit s hould be s et to 1 or hlclk bit is 0, but cks2~cks0 is set to 010, 01 1, 100, 101, 1 10 or 1 11. as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto b it i s c hecked. t he a mount o f t ime r equired f or h igh sp eed sy stem o scillator st abilization depends upon which high speed system oscillator type is used.
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rev. 1.41 42 april 11, 2017 rev. 1.41 43 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom entering the sleep0 mode there is only one way for the devic es to enter the sleep0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the sleep1 mode there is only one way for the devic es to enter the sleep1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he wdt on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the hal t instruction, but the wdt will remain with the clock source coming from the f lirc clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the devic es to enter the idle0 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the t ime base clock f tbc and the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled . ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.41 44 april 11, 2017 rev. 1.41 45 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom entering the idle1 mode there is only one way for the devic es to enter the idle1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 1 a nd t he fsyson bit in ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock and f sub will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt is enabled. ? the i/o ports will maintain their present conditions. ? in the status register , the power down fag, pdf , will be set and the w atchdog time-out fag, t o, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the devices to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit de signer i f t he powe r c onsumption i s t o be m inimised. spe cial a ttention m ust be m ade t o the i/o pins on the devices. all high-impedance input pins must be connected to either a fixed high or low level as any foating input pins could create internal oscillations and result in increased current consumpti on. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must eit her be set up as out puts or if setup as inputs must have pul l-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. t hese shoul d be pl aced i n a c ondition i n whi ch m inimum c urrent i s dra wn or c onnected only to external circuits that do not draw current, such as other cmos inputs. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the devices are woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power-up or executing the clear w atchdog t imer instructions and is set when executing the hal t instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status.
rev. 1.41 44 april 11, 2017 rev. 1.41 45 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wi ll resume exec ution at the i nstruction f ollowing t he halt i nstruction. i f t he sy stem i s wo ken u p by a n i nterrupt, t hen two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. programming considerations the high speed and low speed oscillators both use the same sst counter . for example, if the system is woken up from the sleep0 mode and the hirc oscillators need to start-up from an off state. ? if the devices are woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the devices will execute frst instruction after hto is 1. ? if the devices are woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is 1, the system clock can be switched to the lirc oscillator after wake up. ? there a re p eripheral f unctions, su ch a s tms, f or wh ich t he f sys i s u sed. i f t he sy stem c lock so urce is swi tched f rom f h to f l , t he c lock so urce t o t he p eripheral f unctions m entioned a bove wi ll change accordingly. ? the on/of f condition of f sub depends upon whether the wdt is enabled or disabled as the wdt clock source is sourced from f lirc .
rev. 1.41 46 april 11, 2017 rev. 1.41 47 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer c lock sourc e i s prov ided by t he i nternal f lirc c lock wh ich i s supplied by t he lirc oscillator . the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer tim eouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register . the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v . however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. the wrf software reset fag will be indicated in the ctrl register . this register controls the overall operation of the w atchdog t imer. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we2 we1 we0 ws2 ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function software control 10101: wdt disable 01010: wdt enable other values: reset mcu when thes e bits are changed to any other values by the environmental noise to reset the microcontrolle r, the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1to indicate the reset source. bit 2~0 : wdt t ime-out period selection 000: 2 8 /f lirc 001: 2 10 /f lirc 010: 2 12 /f lirc 011: 2 14 /f lirc 100: 2 15 /f lirc 101: 2 16 /f lirc 110: 2 17 /f lirc 111: 2 18 /f lirc these three bi ts de termine the di vision rat io of the w atchdog t imer sourece clock, which in turn determines the timeout period.
rev. 1.41 46 april 11, 2017 rev. 1.41 47 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 "x": unknown b it 7 : f sys control idle mode 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2 : lvr function reset fag describe elsewhere bit 1 : lvrc register software reset fag describe elsewhere bit 0 : wdtc register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknown location, or enters an endless loop, the clear wdt instructions will not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. w ith regard to the w atchdog t imer enable/disable function, there are fve bits, we4~we0, in the wdtc register to additional enable/disable and reset control of the w atchdog t imer. we4~we0 bits wdt function 10101b disable 01010b enable any other value reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a value other than 01010b and 10101b is written into the we4~we0 bit locations, the second is using the w atchdog t imer software clear instructions and the third is via a hal t instruction. there is only one method of using software instruction to clear the watchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time-out period is when the 2 18 division ratio is selected. as an example, with a 32khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration.
rev. 1.41 48 april 11, 2017 rev. 1.41 49 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom clr wdt instruction 8-stage divider wdt prescaler we4~we0 bits wdtc register reset mcu lirc f lirc f lirc /2 8 8-to-1 mux clr ws2~ws0 wdt time-out (2 8 /f lirc ~ 2 18 /f lirc ) halt instruction watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are several ways in which a microcontroller reset can occur, through events occurring internally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. v dd power-on reset sst time-out t rstd note: t rstd is power-on delay, typical time=50ms power-on reset timing chart
rev. 1.41 48 april 11, 2017 rev. 1.41 49 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom low voltage reset C lvr the microcontrollers contain a low voltage reset circuit in order to monitor the supply voltage of the devices , which is selected via the l vrc register . if the supply voltage of the device drops to within a range of 0.9v~ v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set to1 . f or a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~ v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics . if the low volta ge state does not exceed this value , the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr can be selected by the l vs bits in the l vrc register . if the l vs7~lvs0 bits are changed to som e c ertain va lues by t he e nvironmental noi se, t he l vr wi ll re set t he de vice a fter 2~3 l irc clock cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the regis ter w ill have the value of 01010101b. n ote that the l vr function w ill be automatically disabled when the devices enter the power down mode. lvr internal reset t rstd + t sst note:t rstd is power-on delay, typical time=50ms low voltage reset timing chart ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs3 lvs2 lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 : lvr v oltage select control 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other value: generates mcu reset C register is reset to por value when an actual low voltage condit ion occurs, as specifed by one of the four defned lvr voltage values above, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles. in this situation this register contents will remain the same after such a reset occurs. any r egister v alue, o ther t han t he f our d efned v alues a bove, wi ll a lso r esult i n t he generation o f a n mc u r eset. t he r eset o peration wi ll b e a ctivated a fter 2 ~3 l irc clock cycles. however in this situation this register contents will be reset to the por value.
rev. 1.41 50 april 11, 2017 rev. 1.41 51 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom ? ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 0 0 "x": unknown b it 7 : f sys control idle mode 0: disable 1: enable bit 6~3 unimplemented, read as 0 bit 2 : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 : lvrc register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. this bit can only be cleared to 0 by the application program. bit 0 : wdtc register software reset fag describe elsewhere watchdog time-out reset during normal operation the w atchdog tim e-out reset during normal operation is the same as an l vr reset except that the watchdog time-out fag t o will be set to 1. wdt time-out internal reset t rstd + t sst note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt time-out internal reset t sst note: the t sst is 15~16 clock cycles if the system clock source is provided by the hirc. the t sst is 1024 clock s for hxt. the t sst is 1~2 clock for the lirc. wdt time-out reset during sleep or idle timing chart
rev. 1.41 50 april 11, 2017 rev. 1.41 51 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 power-on reset u u lvr reset during normal or slow mode operation 1 u wdt time-out reset during normal or slow mode operation 1 1 wdt time-out reset during idle or sleep mode operation note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer modules timer modules will be turned off input/output ports i/o ports will be setup as inputs and an0~an4 as a/d input pins stack pointer stack pointer will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. t o ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset af fects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. register HT66F007 ht66f008 reset (power on) lvr reset wdt time-out (normal operation) wdt time-out (halt)* iar0 0000 0000 0000 0000 0000 0000 uuuu uuuu mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu iar1 0000 0000 0000 0000 0000 0000 uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---- --xx ---- --uu ---- --uu ---- --uu ---- xxxx ---- uuuu ---- uuuu ---- uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu integ ---- --00 ---- --00 ---- --00 ---- --uu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 --00 --00 --00 --00 --00 --00 --uu --uu mfi0 --00 --00 --00 --00 --00 --00 --uu --uu mfi1 --00 --00 --00 --00 --00 --00 --uu --uu mfi2 --00 --00 --00 --00 --00 --00 --uu --uu
rev. 1.41 52 april 11, 2017 rev. 1.41 53 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom register HT66F007 ht66f008 reset (power on) lvr reset wdt time-out (normal operation) wdt time-out (halt)* pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu prm 0000 0-00 0000 0-00 0000 0-00 uuuu u-uu lvrc 0101 0101 0101 0101 0101 0101 uuuu uuuu wdtc 0101 0011 0101 0011 0101 0011 uuuu uuuu tbc 0011 -111 0011 -111 0011 -111 uuuu -uuu ctrl 0--- -x00 0--- -yyy 0--- -yyy u--- -uuu eeah ---- ---0 ---- ---0 ---- ---0 ---- ---u ---- --00 ---- --00 ---- --00 ---- --uu eea 0000 0000 0000 0000 0000 0000 uuuu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcr0 0110 -000 0110 -000 0110 -000 uuu- -uuu adcr1 00-0 -000 00-0 -000 00-0 -000 uuuu uuuu acer ---1 1111 ---1 1111 ---1 1111 ---u uuuu cpc 1000 0001 1000 0001 1000 0001 uuuu uuuu tmpc ---0 0101 ---0 0101 ---0 0101 ---u uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu tm2c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm2c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2rp 0000 0000 0000 0000 0000 0000 uuuu uuuu spc ---- 0000 ---- 0000 ---- 0000 ---- uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu note: "*" stands for warm reset "-" not implement "u" stands for "unchanged" "x" stands for "unknown" "y" stands for "by register bit function"
rev. 1.41 52 april 11, 2017 rev. 1.41 53 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the devices provide bidirectional input/output lines labeled with port names p a. these i/o ports are mapped to the ram data memory with specific addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pac pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 papu papu7 papu6 papu5 papu4 papu3 papu2 papu1 papu0 pawu pawu7 pawu6 pawu5 pawu4 pawu3 pawu2 pawu1 pawu0 prm tck1ps1 tck1ps0 tck0ps tp10ps tp01ps intps1 intps0 spc spc3 spc2 spc1 spc0 i/o control register list pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when configured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selecte d using register p apu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name papu7 papu6 papu5 papu4 papu3 papu2 papu1 papu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o port a bit7~bit 0 pull-high control 0: disable 1: enable
rev. 1.41 54 april 11, 2017 rev. 1.41 55 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name pawu7 pawu6 pawu5 pawu4 pawu3 pawu2 pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o port a bit 7~bit 0 w ake up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac, to control the input/output confguration. with this control register , each cm os output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name pac7 pac6 pac5 pac4 pac3 pac2 pac1 pac0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 i/o port a bit 7~bit 0 input/output control 0: output 1: input
rev. 1.41 54 april 11, 2017 rev. 1.41 55 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom special pin control there are four pins, named p a2, p a5, p a6 and p a7, can be set to ttl or cmos input for special applications. spc register bit 7 6 5 4 3 2 1 0 name spc3 spc2 spc1 spc0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3 spc3 : pa7 special pin control 0: cmos input 1: ttl input bit 2 spc2 : pa6 special pin control 0: cmos input 1: ttl input bit 1 spc1 : pa5 special pin control 0: cmos input 1: ttl input bit 0 spc0 : pa2 special pin control 0: cmos input 1: ttl input pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established whe re m ore t han one pi n func tion i s se lected si multaneously. addi tionally t here i s a prm register to establish certain pin functions. generally speaking, the analog function has higher priority t han t he digi tal func tion. howeve r, i f more t han t wo ana log func tions are ena bled and t he analog signal input comes from the same external pin, the analog input will be internally connected to all of these active analog functional modules.
rev. 1.41 56 april 11, 2017 rev. 1.41 57 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom pin-remapping registers the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. ? prm register bit 7 6 5 4 3 2 1 0 name tck1ps1 tck1ps0 tck0ps tp10ps tp01ps intps1 intps0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7~6 tck1ps1, tck1ps0 : tck1 pin-remapping function selection bit 00: tck1 on pa2 01: tck1 on pa7 10: undefned 11: tck1 on pa4 bit 5 tck0ps : tck0 pin-remapping function selection bit 0: tck0 on pa7 1: tck0 on pa6 bit 4 tp10ps : tp1_0 pin-remapping function selection bit 0: tp1_0 on pa6 1: tp1_0 on pa7 bit 3 tp01ps : tp0_1 pin-remapping function selection bit 0: tp0_1 on pa5 1: tp0_1 on pa1 bit 2 unimplemented, read as 0 bit 1~0 intps1, intps0 : int pin-remapping function selection bit 00: int on pa5 01: int on pa2 10: int on pa3 11: int on pa7
rev. 1.41 56 april 11, 2017 rev. 1.41 57 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ?? ? ? ? generic input/output structure

? ? ? ?
? ? - ? ? ? ? ? ? ?? - a/d input/output structure
rev. 1.41 58 april 11, 2017 rev. 1.41 59 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control register , p ac, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register , p a, is frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. the power -on reset condition of the a/d converter control registers ensures that any a/d input pins whi ch a re a lways sha red wi th ot her i/ o func tions wi ll be se tup a s a nalog i nputs a fter a re set. although these pins will be confgurated as a/d inputs after a reset, the a/d converter will not be switched on. it i s t herefore i mportant t o not e t hat i f i t i s re quired t o use t hese pi ns a s i/ o di gital input pins or as other functions, the a/d converter control registers must be correctly programmed to remove the a/d funct ion. note al so that as the a/d channe l is enabled, any inte rnal pul l-high registor connections will be removed. port a has the additional capability of providing wake-up functions. when the devices are in the sleep or idle mode, various methods are available to wake the devices up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.41 58 april 11, 2017 rev. 1.41 59 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions the devices include several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, compare match output and single pulse output as well as being t he fu nctional u nit fo r t he g eneration o f pw m si gnals. e ach o f t he t ms h as t wo i ndividual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact and standard tm sections. introduction each device contains two 10-bit compact tms and a 16-bit standard tm, the 10-bit ctms are named to tm0 and tm1, the 16-bit stm is named to tm2. although similar in nature, the dif ferent tm types vary in their feature complexity . the common features to the compact and standard tms will be described in this section and the detailed operation will be described in corresponding sections. t he m ain fe atures a nd di fferences be tween t he t wo t ypes of t ms a re sum marised i n t he accompanying table. function ctm stm timer/counter compare match output pwm channels 1 1 single pulse output 1 pwm alignment edge edge pwm adjustment period & duty duty or period duty or period tm function summary tm0 tm1 tm2 10-bit ctm 10-bit ctm 16-bit stm tm name/type reference tm operation the t wo d ifferent t ypes o f t ms o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin.
rev. 1.41 60 april 11, 2017 rev. 1.41 61 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setti ng these bits to the value 101 will selec t a reserved clock input, in ef fect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each has two internal interrupts, the internal comparator a or com parator p , whi ch ge nerate a tm interrupt when a com pare match condition oc curs. whe n a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tms each have one or more output pins. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must firs t be setup using registers. a single bit in one of the registers determines if its associated pi n i s t o be use d a s a n e xternal t m out put pi n or i f i t i s t o ha ve a nother func tion. t he number of output pins for each tm type is dif ferent, the details are provided in the accompanying table. both ctm and stm output pin names have an _n suffx. pin name s that include a _0 or _1 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complementary output pair, selected using the i/o register data bits. tm0 tm1 tm2 tp0_0, tp0_1 tp1_0, tp1_1 tp2_0 tm output pins note: the tp2_1 pin of stm is not bonded to the external tm output pin.
rev. 1.41 60 april 11, 2017 rev. 1.41 61 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom tm input/output pin control register selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function.

tm0 function pin control block diagram

tm1 function pin control block diagram
rev. 1.41 62 april 11, 2017 rev. 1.41 63 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom

tm2 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. for the tm2, the tp2_1 pin is not bonded to the external pin. 3. the above diagrams do not include the pin-remapping function, refer to the prm register for the pin-remapping function. tmpc register bit 7 6 5 4 3 2 1 0 name t2cp0 t1cp1 t1cp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w por 0 0 1 0 1 bit 7~5 unimplemented, read as 0 bit 4 t2cp0 : tp2_0 pin control 0: disable 1: enable bit 3 t1cp1 : tp1_1 pin control 0: disabled 1: enabled bit 2 t1cp0 : tp1_0 pin control 0: disabled 1: enabled bit 1 t0cp1 : tp0_1 pin control 0: disabled 1: enabled bit 0 t0cp0 : tp0_0 pin control 0: disabled 1: enabled
rev. 1.41 62 april 11, 2017 rev. 1.41 63 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom programming considerations the tm counter registers and the compare ccra register , being either 10-bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as t he ccra re gister i s i mplemented i n t he wa y shown i n t he fol lowing di agram a nd a ccessing this register is carried out in a specifc way described above, it is recommended to use the mov instruction t o a ccess t he c cra l ow b yte r egister, n amed t mxal, i n t he f ollowing a ccess procedures. accessing the ccra low byte register without following these access procedures will result in unpredictable values. data bus 8-bit buffer tmxdh tmxdl tmxah tmxal tm counter register (read only) tm ccra register (read/write) the following steps show the read and write procedures: ? writing data to ccra ? step 1. w rite data to low byte tmxal C note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah C here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra ? step 1. read data from the high byte tmxdh, tmxah C here d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal C this step reads data from the 8-bit buffer.
rev. 1.41 64 april 11, 2017 rev. 1.41 65 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom compact type tm C ctm although the simplest form of the two t m types, the compact t m type still contains three operating modes, wh ich a re c ompare ma tch ou tput, t imer/event c ounter a nd pw m ou tput m odes. t he compact tm can also be controlled with an external input pin and can drive one or two external output pins. these two external output pins can be the same signal or the inverse signal.
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? - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ? - compact type tm block diagram (n=0, 1) compact type tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control two output pins. all operating setup conditions are selected using relevant internal registers.
rev. 1.41 64 april 11, 2017 rev. 1.41 65 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom compact type tm register description overall ope ration of e ach com pact t m i s c ontrolled usi ng se veral re gisters. a re ad onl y re gister pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. register name bit 7 6 5 4 3 2 1 0 tmpc t2cp0 t1cp1 t1cp0 t0cp1 t0cp0 tmnc0 tnpau tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d5 d4 d3 d2 d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d4 d3 d2 d1 d0 tmnah d9 d8 compact type tm register list (n=0, 1) tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 101: f tbc 110: tc kn rising edge clock 111: tc kn falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section.
rev. 1.41 66 april 11, 2017 rev. 1.41 67 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t ncclr bi t i s se t t o zero. set ting t he t ncclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.41 66 april 11, 2017 rev. 1.41 67 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these b its se tup t he r equired o perating m ode f or t he t m. t o e nsure r eliable o peration t he tm sh ould b e swi tched o ff b efore a ny c hanges a re m ade t o t he b its. i n t he t imer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tmn output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the tnio1~tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the tnio1~tnio0 bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit. note that the output level requested by the tnio1~tnio0 bits must be dif ferent from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. af ter t he t m o utput p in c hanges st ate i t c an b e r eset t o i ts i nitial l evel b y changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the tnio1 and tnio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running.
rev. 1.41 68 april 11, 2017 rev. 1.41 69 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom bit 3 tnoc : tmn output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tmn output polarity control 0: non-invert 1: invert this bit controls the polarity of the tm output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode.
rev. 1.41 68 april 11, 2017 rev. 1.41 69 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl : tmn counter low byte register bit 7~bit 0 tmn 10-bit counter bit 7~bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmndh : tmn counter high byte register bit 1~bit 0 tmn 10-bit counter bit 9~bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal : tmn ccra low byte register bit 7~bit 0 tmn 10-bit ccra bit 7~bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tmnah : tmn ccra high byte register bit 1~bit 0 tmn 10-bit ccra bit 9~bit 8
rev. 1.41 70 april 11, 2017 rev. 1.41 71 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm output mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t naf a nd t npf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.41 70 april 11, 2017 rev. 1.41 71 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0; tnm [1:0] = 00 output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon bit rising edge 4. n=0 or 1
rev. 1.41 72 april 11, 2017 rev. 1.41 73 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom counter value 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change tncclr = 1; tnm [1:0] = 00 compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon rising edge 4. the tnpf fags is not generated when tncclr=1 5. n=0 or 1
rev. 1.41 72 april 11, 2017 rev. 1.41 73 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t ncclr bi t ha s no e ffect a s t he pw m period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ? ctm, pwm mode, edge-aligned mode, tndpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys =16mhz, tm clock source is f sys /4, ccrp= 100b, ccra=128, the c tm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/ 512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? ctm, pwm mode, edge-aligned mode, tndpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.41 74 april 11, 2017 rev. 1.41 75 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom counter value ccrp ccra tnon tnpau tnpol tm o/p pin (tnoc=1) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) ccra int. flag tnaf ccrp int. flag tnpf tndpx = 0; tnm [1:0] = 10 pwm mode C tndpx=0 note: 1. here tndpx=0 - counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues running even when tnio[1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0 or 1
rev. 1.41 74 april 11, 2017 rev. 1.41 75 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high pwm duty cycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) tndpx = 1; tnm [1:0] = 10 pwm mode C tndpx=1 note: 1. here tndpx=1 - counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio[1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=0 or 1
rev. 1.41 76 april 11, 2017 rev. 1.41 77 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom standard type tm C stm the standard t ype tm contains four operating modes, which are compare match output, t imer/ event counter , single pulse output and pwm output modes. the standard tm can drive one external output pin.
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? ? ? ??? ?? ? ??? ? ? ? ? ? ? ? ? ? ? ?? ? ?- ? ?? ? ?- ? ?? ? ?- note: tpn_1 (n=2) pin is not connected to the external pin. standard type tm block diagram (n=2) standard type tm operation at its core is a 16-bit count-up counter which is driven by a user selectable internal clock source. there are also tw o internal comparators w ith the names , comparator a and comparator p . these comparators will compare the value in the counter with ccrp and ccra registers. t he ccrp is 8-bit wide whose value is compared with the highest 8 bits in the counter while the ccra is the sixteen bits and therefore compares with all counter bits. the onl y way of changing the value of the 16-bit counte r using the appl ication program , is to clear the counter by changing the t2on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.41 76 april 11, 2017 rev. 1.41 77 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom standard type tm register description overall operation of the standard tm is controlled using series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 16 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 16-bit ccra value. a read/write register is used to store the 8-bit ccrp value. the remaining two registers are control registers which setup the different operating and control modes. register name bit 7 6 5 4 3 2 1 0 tm2c0 t2pau t2ck2 t2ck1 t2ck0 t2on tm2c1 t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr tm2dl d7 d6 d5 d4 d3 d2 d1 d0 tm2dh d15 d14 d13 d12 d11 d10 d9 d8 tm2al d7 d6 d5 d4 d3 d2 d1 d0 tm2ah d15 d14 d13 d12 d11 d10 d9 d8 tm2rp d7 d6 d5 d4 d3 d2 d1 d0 16-bit standard type tm register list tm2c0 register bit 7 6 5 4 3 2 1 0 name t2pau t2ck2 t2ck1 t2ck0 t2on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 t2pau : tm2 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2~t2ck0 : select tm2 counter clock 000: f /4 001: f 010: f /16 011: f /64 100: f tbc 101: reserved 110: reserved 111: reserved these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter . the clock source f is the system c lock, wh ile f a nd f tbc a re o ther i nternal c locks, t he d etails o f wh ich c an b e found in the oscillator section.
rev. 1.41 78 april 11, 2017 rev. 1.41 79 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom bit 3 t2on : tm2 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run, cle aring the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t2oc bit, when the t2on bit changes from low to high. bit 2~0 unimplemented, read as "0" tm2c1 register bit 7 6 5 4 3 2 1 0 name t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t2m1~t2m0 : select tm2 operating mode 00: compare match output mode 01: undefned 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the bits. in the t imer/ counter mode, the tm output pin control must be disabled. bit 5~4 t2io1~t2io0 : select tm2 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.41 78 april 11, 2017 rev. 1.41 79 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom in the compare match output mode, the t2io1~t2io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the t2io1~t2io0 bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2oc bit. note that the output level requested by the t2io1~t2io0 bits must be dif ferent from the initial value setup using the t2oc bit otherwise no change will occur on the tm output pin when a compare match occurs. af ter t he t m o utput p in c hanges st ate i t c an b e r eset t o i ts i nitial l evel b y changing the level of the t2on bit from low to high. in the pwm mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the t2io1 and t2io0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t2io1 and t2io0 bits are changed when the tm is running. bit 3 t2oc : tm2 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2pol : tm2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tm output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm is in the t imer/counter mode. bit 1 t2dpx : tm2 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t2cclr : select tm2 counter clear condition 0: tm comparatror p match 1: tm comparatror a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he standard tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t2cclr bit is not used in the pwm or single pulse mode.
rev. 1.41 80 april 11, 2017 rev. 1.41 81 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom tm2dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dl : tm2 counter low byte register bit 7~bit 0 tm2 16-bit counter bit 7~bit 0 tm2dh register bit 7 6 5 4 3 2 1 0 name d15 d14 d13 d12 d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dh : tm2 counter high byte register bit 7~bit 0 tm2 16-bit counter bit 15~bit 8 tm2al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2al : tm2 ccra low byte register bit 7~bit 0 tm2 16-bit ccra bit 7~bit 0 tm2ah register bit 7 6 5 4 3 2 1 0 name d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2ah : tm2 ccra high byte register bit 7~bit 0 tm2 16-bit ccra bit 15~bit 8 tm2rp register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2rp : tm2 ccrp high byte register bit 7~bit 0 tm2 ccrp 8-bit register, compared with the tm2 counter bit 15~bit 8. comparator p match period 0: 65536 tm2 clocks 1~255: 256 (1~255) tm2 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register , which are then compared with the internal counter s highest eight bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 2cclr bi t i s se t t o zero. set ting t he t 2cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing a ll e ight bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.41 80 april 11, 2017 rev. 1.41 81 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom standard type tm operating modes the standard t ype tm can operate in one of four operating modes, compare match output mode, pwm output mode, single pulse output mode or t imer/counter mode. the operating mode is selected using the t2m1 and t2m0 bits in the tm2c1 register. compare match output mode to select this mode, bits t2m1 and t2m0 in the tm2c1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the t2cclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t 2af a nd t 2pf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the t2cclr bit in the tm2c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t2af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t2cclr i s h igh n o t 2pf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t2af interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t 2pf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he t2io1 and t2io0 bits in the tm2c1 register . the tm output pin can be selected using the t2io1 and t2io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he t2on bit changes from low to high, is setup using the t2oc bit. note that if the t2io1 and t2io0 bits are zero then no pin change will take place.
rev. 1.41 82 april 11, 2017 rev. 1.41 83 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom ccrp int. flag tnpf ccra int. flag tnaf counter value 0xffff ccrp ccra tnon tnpau tnpol time ccrp=0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high tncclr = 0; tnm [1:0] = 00 compare match output mode C tncclr=0 note: 1. w ith tncclr=0 a comparator p match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon bit rising edge 4. n=2
rev. 1.41 82 april 11, 2017 rev. 1.41 83 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom counter value 0xffff ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin time ccra=0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart output pin set to initial level low if tnoc=0 output toggle with tnaf flag note tnio [1:0] = 10 active high output select here tnio [1:0] = 11 toggle output select output not affected by tnaf flag. remains high until reset by tnon bit output pin reset to initial value output controlled by other pin-shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change tncclr = 1; tnm [1:0] = 00 compare match output mode C tncclr=1 note: 1. w ith tncclr=1 a comparator a match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon rising edge 4. the tnpf fags is not generated when tncclr=1 5. n=2
rev. 1.41 84 april 11, 2017 rev. 1.41 85 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom timer/counter mode to select this mode, bits t2m1 and t2m0 in the tm2c1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to se lect t his mode , bit s t2m1 and t 2m0 i n t he t m2c1 regi ster shoul d be se t t o 10 respe ctively and also the t2io1 and t2io0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t 2cclr bi t ha s no e ffect a s t he pw m period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the t2dpx bit in the tm2c1 register. the pw m wa veform f requency a nd d uty c ycle c an t herefore b e c ontrolled b y t he v alues i n t he ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t2oc bit in the tm2c1 register is used to select the required polarity of the pwm waveform while the two t2io1 and t2io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t2pol bit is used to reverse the polarity of the pwm output waveform. ? 16-bit stm, pwm mode, edge-aligned mode, t2dpx=0 ccrp 1~255 0 period ccrp256 65536 duty ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=2 and ccra=128, the stm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125khz, duty=128/ 512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ? 16-bit stm, pwm mode, edge-aligned mode, t2dpx=1 ccrp 1~255 0 period ccra duty ccrp256 65536 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the (ccrp256) except when the ccrp value is equal to 0.
rev. 1.41 84 april 11, 2017 rev. 1.41 85 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom counter value ccrp ccra tnon tnpau tnpol tm o/p pin (tnoc=1) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high pwm duty cycle set by ccra pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccrp tm o/p pin (tnoc=0) ccra int. flag tnaf ccrp int. flag tnpf tndpx = 0; tnm [1:0] = 10 pwm mode C tndpx=0 note: 1. here tndpx=0 - counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues running even when tnio[1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=2
rev. 1.41 86 april 11, 2017 rev. 1.41 87 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high pwm duty cycle set by ccrp pwm resumes operation output controlled by other pin-shared function output inverts when tnpol = 1 pwm period set by ccra tm o/p pin (tnoc=0) tndpx = 1; tnm [1:0] = 10 pwm mode C tndpx=1 note: 1. here tndpx=1 - counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio[1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=2
rev. 1.41 86 april 11, 2017 rev. 1.41 87 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom single pulse mode to se lect t his mode , bit s t 2m1 and t 2m0 i n t he t m2c1 regi ster should be se t t o 10 respe ctively and also the t2io1 and t2io0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the t2on bit, which can be implem ented using the applicati on program. when the t2on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the t2on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the t2on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a.

?? ? ? ? ? single pulse generation (n=2) however a compare match from comparator a will also automatically clear the t2on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the t2on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t2cclr and t2dpx bits are not used in this mode.
rev. 1.41 88 april 11, 2017 rev. 1.41 89 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom counter value ccrp ccra tnon tnpau tnpol ccrp int. flag tnpf ccra int. flag tnaf tm o/p pin (tnoc=1) time counter stopped by ccra pause resume counter stops by software counter reset when tnon returns high pulse width set by ccra output inverts when tnpol = 1 no ccrp interrupts generated tm o/p pin (tnoc=0) software trigger cleared by ccra match software clear software trigger software trigger tnm [1:0] = 10 ; tnio [1:0] = 11 software trigger software trigger cleared by ccra match single pulse mode note: 1. counter stopped by ccra match 2. ccrp is not used 3. the pulse is triggered by setting the tnon bit high 4. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. 5. n=2
rev. 1.41 88 april 11, 2017 rev. 1.41 89 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. input channels a/d channel select bits input pins 5 acs4, acs2~acs0 an0~an4 the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers.
? ?? ? ?? ?? ? ?? ?? ? - ? ?? ? ? - ? ? ? ? - ? ?
? ?? ? ?? ? ? ? ? ? ?-? ? a/d converter structure a/d converter register description overall operation of the a /d converter is controlled us ing f ve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d3 d2 d1 d0 adrl(adrfs=1) d7 d6 d5 d4 d3 d2 d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs2 acs1 acs0 adcr1 acs4 vbgen vrefs adck2 adck1 adck0 acer ace4 ace3 ace2 ace1 ace0 a/d converter register list
rev. 1.41 90 april 11, 2017 rev. 1.41 91 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter , it requires two data registers to store the converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow by te re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acer to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1, acer are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter , the digitise d data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs2~acs0 bits in the adcr0 register and the acs4 bit in the adcr1 register defne the adc input channel number . as the devices contain only one actual analog to digital converter hardware c ircuit, e ach of t he i ndividual 5 a nalog i nputs m ust be ro uted t o t he c onverter. it i s t he function of the acs4, acs2~acs0 bits to determine which analog channel input signals or internal 1.25v is actually connected to the internal a/d converter. the ac er c ontrol r egister c ontains t he ac e4~ace0 b its wh ich d etermine wh ich p ins o n po rt a are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corres ponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.41 90 april 11, 2017 rev. 1.41 91 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom adcr0 register bit 7 6 5 4 3 2 1 0 name start eocb adoff adrfs acs2 acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 bit 7 start : start the a/d conversion 010: start 01: reset the a/d converter and set eocb to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 unimplemented, read as 0 bit 2~0 acs2~acs0 : select a/d channel (when acs4 is 0) 000: an0 001: an1 010: an2 011: an3 others: an4 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter.
rev. 1.41 92 april 11, 2017 rev. 1.41 93 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom adcr1 register bit 7 6 5 4 3 2 1 0 name acs4 vbgen vrefs adck2 adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4 : selecte internal 1.25v as adc input control 0: disable 1: enable this bit enables 1.25v to be connected to the a/d converter . the vbgen bit must frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 vbgen : internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap 1.25v voltage can be used by the a/d converter . if 1.25v is not used by the a/d converter and the l vr function is disabled then the bandgap reference circuit will be automatically switched of f to conserve power . when 1.25v is switched on for use by the a/d converter , a time tbg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as 0 bit 4 vrefs : selecte adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low then the internal referenc e is used which is taken from the power supply pin vdd. when the a/d converter reference voltage is supplied on the external vref pin which is pin-shared with other functions, all of the pin-shared function s except vref on this pin are disabled. bit 3 unimplemented, read as 0 bit 2~0 adck2~adck0 : select adc clock source 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: undefned these three bits are used to select the clock source for the a/d converter.
rev. 1.41 92 april 11, 2017 rev. 1.41 93 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom acer register bit 7 6 5 4 3 2 1 0 name ace4 ace3 ace2 ace1 ace0 r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 bit 7~5 unimplemented, read as 0 bit 4 ace4 : defne pa5 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pa3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bi t i n t he adcr0 regi ster i s use d t o i ndicate whe n t he ana log t o digi tal conve rsion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow t o t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f , can be chosen to be either f or a subdivided version of f . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/ d clock source is determined by the system clock f , and by bits adck2~adck0, there a re so me l imitations o n t he m aximum a/ d c lock so urce sp eed t hat c an b e se lected. as t he recommended range of permissible a/d clock period, t adck , is from 0.5s to 10 s, care must be taken for system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 1 10b . doing so will give a/d clock periods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d c lock period which may result in inaccurate a/d conversion values.
rev. 1.41 94 april 11, 2017 rev. 1.41 95 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom refer t o t he fol lowing t able for e xamples, whe re va lues m arked wi th a n a sterisk * sh ow whe re, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s 2s 4s 8s 16s* 32s* 64s* undefned 2mhz 500ns 1s 2s 4s 8s 16s* 32s* undefned 4mhz 250ns* 500ns 1s 2s 4s 8s 16s* undefned 8mhz 125ns* 250ns* 500ns 1s 2s 4s 8s undefned 12mhz 83ns* 167ns* 333ns* 667ns 1.33s 2.67s 5.33s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace4~ace0 bits in the acer registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of t he a/ d a nalog i nput pi ns a re pi n-shared wi th t he i/ o pi ns on por t a a s we ll a s ot her functions. the ace4~ace0 bits in the acer registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace4~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way , pins can be changed under program control to change their function bet ween a/ d input s and othe r func tions. al l pull -high resi stors, whi ch are se tup t hrough register programm ing, will be autom atically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p ac port control register to enable the a/d input as when the ace4~ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of v ref.
rev. 1.41 94 april 11, 2017 rev. 1.41 95 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom
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? a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4, acs2~acs0 bits which are also contained in the adcr1 and adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace4~ace0 bits in the acer register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when t his bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the met hod of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck where t adck is equal to the a/d clock period.
rev. 1.41 96 april 11, 2017 rev. 1.41 97 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom

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? ? ? ? ? ? ? ? ? ? ? a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing used, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb=(v dd or v ref )/4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage=a/d output digital value (v dd or v ref )/4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.
rev. 1.41 96 april 11, 2017 rev. 1.41 97 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom

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? ideal a/d transfer function a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr a de ; disable adc interrupt mov a,03h mov adcr1,a ; s elect f sys /8 as a /d c lock a nd s witch o ff 1 .25v clr adoff mov a,0fh ; s etup ac er t o c onfgure p ins a n0~an3 mov acer,a mov a,00h mov adcr0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter : start_conversion: clr start ; h igh p ulse o n s tart b it t o i nitiate c onversion set start ; r eset a /d clr start ; s tart a /d polling_eoc: sz eocb ; p oll t he a dcr0 r egister e ocb b it t o d etect e nd o f a /d c onversion jmp polling_eoc ; c ontinue p olling mov a,adrl ; re ad l ow b yte c onversion re sult v alue mov adrl_buffer,a ; s ave r esult t o us er d efned r egister mov a,adrh ; re ad h igh b yte c onversion re sult v alue mov adrh_buffer,a ; s ave r esult t o us er d efned r egister : : jmp start_conversion ; s tart n ext a/ d c onversion
rev. 1.41 98 april 11, 2017 rev. 1.41 99 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a /d c lock a nd s witch o ff 1 .25v clr adoff mov a,0fh ; s etup a cer t o c onfgure p ins a n0~an3 mov acer,a mov a,00h mov adcr0,a ; e nable an d c onnect a n0 c hannel t o a /d c onverter start_conversion: clr start ; h igh p ulse o n st art b it t o i nitiate c onversion set start ; r eset a /d clr start ; s tart a /d clr adf ; c lear a dc i nterrupt r equest f ag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; s ave ac c t o u ser d efned m emory mov a,status mov status_stack,a ; s ave st atus t o us er d efned m emory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; s ave r esult t o us er d efned r egister mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; s ave r esult t o us er d efned r egister : : exit_int_isr: mov a,status_stack mov status,a ; restore s tatus f rom u ser d efned m emory mov a,acc_stack ; re store a cc f rom u ser d efned m emory reti
rev. 1.41 98 april 11, 2017 rev. 1.41 99 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom comparator one independent analog comparato r is contained within the devices. this function of fers fexibility via its register controlled features such as power -down, polarity select, hysteresis etc. in sharing its pins with normal i/o pins the comparator does not waste precious i/o pins if there functions are otherwise unused. comparator operation the devices contain one comparator which is used to compare two analog voltages and provide an output based on their dif ference. full control over the internal comparator is provided via the control register, cpc. the comparator output is recorded via a bit in the control register, but can also be transferred out onto a shared i/o pin. additional comparator functions include, output polarity , hysteresis functions and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, so me sp urious o utput si gnals m ay b e g enerated o n t he c omparator o utput d ue t o t he sl ow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator . ideally the comparator should swi tch a t t he poi nt whe re t he posi tive a nd ne gative i nputs si gnals a re a t t he sa me vol tage level, however , unavoidable input of fsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. comparator register there is one register for overall comparator operation. cpc register bit 7 6 5 4 3 2 1 0 name csel cen cpol cout cos cinte1 cinte0 chyen r/w r/w r/w r/w r r/w r/w r/w r/w por 1 0 0 0 0 0 0 1 bit 7 csel : select comparator pins or i/o pins 0: i/o pins select 1: comparator input pins cp and cn selected this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 cen : comparator on/off control 0: off 1: on this i s t he com parator on/ off c ontrol bi t. if t he bi t i s z ero t he c omparator wi ll be switched of f and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the devices enter the sleep or idle mode.
rev. 1.41 100 april 11, 2017 rev. 1.41 101 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom bit 5 cpol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the cout bit will refect the non-inverted output condition of the comparator . if the bit is high the comparator cout bit will be inverted. bit 4 cout : comparator output bit cpol=0 0: cp < cn 1: cp > cn cpol=1 0: cp > cn 1: cp < cn this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the cpol bit. bit 3 cos : comparator output path select 0: cx pin 1: internal use this is the comparator output path select control bit. if the bit is set to 0 and the csel bit is 1 the comparator output is connected to an external cx pin. if the bit is set to 1 or the csel bit is 0 the comparator output signal is only used internally by the device allow ing the s hared comparator output pin to retain its normal i/o operation. bit 2~1 cinte1, cinte0 : comparator interrupt edge control 00: rising edge 01: falling edge 1x: rising edge and falling edge bit 0 chyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator , as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the ef fect of spurious switching near the comparator threshold. comparator interrupt the comparator possesses its own interrupt function. when the comparator output bit changes state, its releva nt interru pt fag will be set, and if the corresponding interrupt enable bit is set, then a jump to its rele vant inte rrupt vector will be executed. note that it is the changing state of the cout bit and not the output pin which generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output bit to change state, the resulting generated interrupt fag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be set high before entering the sleep or idle mode. programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power , the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control register is 1) or read as port data register value (port control register is 0) if the comparator function is enabled.
rev. 1.41 100 april 11, 2017 rev. 1.41 101 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the devices contain an external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int pin, while the internal interrup ts are generated by various interna l functions such as the tms, comparator, t ime base, eeprom and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the interrupt registers fall into three categories. the frst is the intc0~intc2 registers which setup the primary interrupts, the second is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global emi int pin inte intf a/d converter ade adf multi-function mfne mfnf n=0~2 comparator cpe cpf time base tbne tbnf n=0 or 1 eeprom dee def tm tnpe tnpf n=0~2 tnae tnaf interrupt register bit naming conventions register name bit 7 6 5 4 3 2 1 0 integ ints1 ints0 intc0 mf0f tb0f intf mf0e tb0e inte emi intc1 tb1f adf def mf1f tb1e ade dee mf1e intc2 mf2f cpf mf2e cpe mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi2 t2af t2pf t2ae t2pe interrupt register contents
rev. 1.41 102 april 11, 2017 rev. 1.41 103 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom integ register bit 7 6 5 4 3 2 1 0 name ints1 ints0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 ints1, ints0 : defnes int interrupt active edge 00: disabled interrupt 01: rising edge interrupt 10: falling edge interrupt 11: dual edge interrupt intc0 register bit 7 6 5 4 3 2 1 0 name mf0f tb0f intf mf0e tb0e inte emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf0f : multi-function 0 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f : t ime base 0 interrupt request flag 0: no request 1: interrupt request bit 4 intf : int interrupt request flag 0: no request 1: interrupt request bit 3 mf0e : multi-function 0 interrupt control 0: disable 1: enable bit 2 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 1 inte : int interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
rev. 1.41 102 april 11, 2017 rev. 1.41 103 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom intc1 register bit 7 6 5 4 3 2 1 0 name tb1f adf def mf1f tb1e ade dee mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb1f : t ime base 1 interrupt request flag 0: no request 1: interrupt request bit 6 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request flag 0: no request 1: interrupt request bit 4 mf1f : multi-function 1 interrupt request flag 0: no request 1: interrupt request bit 3 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 2 ade : a/d converter interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 mf1e : multi-function 1 interrupt control 0: disable 1: enable intc2 register bit 7 6 5 4 3 2 1 0 name mf2f cpf mf2e cpe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 mf2f : multi-function 2 interrupt request flag 0: no request 1: interrupt request bit 4 cpf : comparator interrupt request flag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 mf2e : multi-function 2 interrupt control 0: disable 1: enable bit 0 cpe : comparator interrupt control 0: disable 1: enable
rev. 1.41 104 april 11, 2017 rev. 1.41 105 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom mfi0 register bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 name t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.41 104 april 11, 2017 rev. 1.41 105 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom mfi2 register bit 7 6 5 4 3 2 1 0 name t2af t2pf t2ae t2pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 0 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/ d conversion completion etc, the relevant interrupt request fag wi ll be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter address from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded.
rev. 1.41 106 april 11, 2017 rev. 1.41 107 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. 04h 08h 0ch 18h vector low priority high request flags enable bits master enable request flags enable bits emi auto disabled in isr interrupts contained within multi - function interrupts interrupt name interrupt name emi emi emi def eeprom dee t0af tm0 a t0ae t0pf tm0 p t0pe intf int pin inte cpf comparator cpe mf0f m. funct. 0 mf0e adf a/d ade emi tb0f time base 0 tb0e xxf legend request flag C no auto reset in isr xxf request flag C auto reset in isr xxe enable bit t1af tm1 a t1pf tm1 p t1ae t1pe emi tb1f time base 1 tb1e t2af tm2 a t2ae t2pf tm2 p t2pe 24h emi mf2f m. funct. 2 mf2e 10h emi mf1f m. funct. 1 mf1e 14h emi 1ch 20h emi interrupt structure
rev. 1.41 106 april 11, 2017 rev. 1.41 107 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom external interrupt the external interrupt is controlled by signal transitions on the pins int . an external interrupt request will take place when the external interrupt request fag, intf , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. t o allow the program to branch to the interrupt vector address, the global interrupt enable bit, emi, and the extern al interr upt enable bit, inte, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pin is pin-s hared with an i/o pin, it can only be confgured as exte rnal interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fag, intf , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that the pull-high resistor selection on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. comparator interrupt the comparator interrupt is controlled by the internal comparator . a comparator interrupt request will take place when the comparator interrupt request fag, cpf , is set, a situation that will occur when the comparator output bit changes state. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bit, cpe, must frst be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector , will take place. when the interrupt is serviced, the comparator interrupt request flag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt within these devices there are up to three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf2f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupt s, will not be automatically reset and must be manually reset by the application program.
rev. 1.41 108 april 11, 2017 rev. 1.41 109 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom a/d converter interrupt the devices conta in an a/d converter which has its own independent interrupt. the a/d converter interrupt is controlled by the termin ation of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must frst be set. when the inte rrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converte r interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt flag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section.
rev. 1.41 108 april 11, 2017 rev. 1.41 109 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 1 1 1 bit 7 tbon : tb0 and tb1 control bit 0: disable 1: enable it 6 tbck : select f clock 0: f tbc 1: f /4 bit 5~4 tb11~tb10 : select t ime base 1 t ime-out period 00: 4096/f 01: 8192/f 10: 16384/f 11: 32768/f bit 3 unimplemented, read as 0 bit 2~0 tb02~tb00 : select t ime base 0 t ime-out period 000: 256/f 001: 512/f 010: 1024/f 011: 2048/f 100: 4096/f 101: 8192/f 110: 16384/f 111: 32768/f

time base interrupt
rev. 1.41 110 april 11, 2017 rev. 1.41 111 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom eeprom interrupt an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom w rite cycle ends. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and eeprom interrupt enable bit, dee, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vect or, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, and the eeprom interrupt request fag, def, will also be automatically cleared. tm interrupts the compact and standard t ype tms each has two interrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and standard t ype tms there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request flags are set, a situation which occurs when a tm comparator p or comparator a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the respective tm interrupt enable bit, and associated multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant tm interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function.
rev. 1.41 110 april 11, 2017 rev. 1.41 111 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the m ulti-function interrupt reques t f ags, m f0f~mf2f, w ill be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.41 112 april 11, 2017 rev. 1.41 113 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator option 1 high speed/low speed system oscillator selection C f osc : 1. hirc+lirc 2. hxt+lirc 2 hirc frequency selection: 1. 4mhz 2. 8mhz 3. 12mhz application circuits

rev. 1.41 112 april 11, 2017 rev. 1.41 113 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom instruction set instruction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtekmicrocontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.41 114 april 11, 2017 rev. 1.41 115 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they dif fer in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f poi nt as in the case of the call instruct ion. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.41 114 april 11, 2017 rev. 1.41 115 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] add data memory to acc 1 z, c, ac, ov addm a,[m] add acc to data memory 1 note z, c, ac, ov add a,x add immediate data to acc 1 z, c, ac, ov adc a,[m] add data memory to acc with carry 1 z, c, ac, ov adcm a,[m] add acc to data memory with carry 1 note z, c, ac, ov sub a,x subtract immediate data from the acc 1 z, c, ac, ov sub a,[m] subtract data memory from acc 1 z, c, ac, ov subm a,[m] subtract data memory from acc with result in data memory 1 note z, c, ac, ov sbc a,[m] subtract data memory from acc with carry 1 z, c, ac, ov sbcm a,[m] subtract data memory from acc with carry, result in data memory 1 note z, c, ac, ov daa [m] decimal adjust acc for addition with result in data memory 1 note c logic operation and a,[m] logical and data memory to acc 1 z or a,[m] logical or data memory to acc 1 z xor a,[m] logical xor data memory to acc 1 z andm a,[m] logical and acc to data memory 1 note z orm a,[m] logical or acc to data memory 1 note z xorm a,[m] logical xor acc to data memory 1 note z and a,x logical and immediate data to acc 1 z or a,x logical or immediate data to acc 1 z xor a,x logical xor immediate data to acc 1 z cpl [m] complement data memory 1 note z cpla [m] complement data memory with result in acc 1 z increment & decrement inca [m] increment data memory with result in acc 1 z inc [m] increment data memory 1 note z deca [m] decrement data memory with result in acc 1 z dec [m] decrement data memory 1 note z rotate rra [m] rotate data memory right with result in acc 1 none rr [m] rotate data memory right 1 note none rrca [m] rotate data memory right through carry with result in acc 1 c rrc [m] rotate data memory right through carry 1 note c rla [m] rotate data memory left with result in acc 1 none rl [m] rotate data memory left 1 note none rlca [m] rotate data memory left through carry with result in acc 1 c rlc [m] rotate data memory left through carry 1 note c
rev. 1.41 116 april 11, 2017 rev. 1.41 117 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom mnemonic description cycles flag affected data move mov a,[m] move data memory to acc 1 none mov [m],a move acc to data memory 1 note none mov a,x move immediate data to acc 1 none bit operation clr [m].i clear bit of data memory 1 note none set [m].i set bit of data memory 1 note none branch operation jmp addr jump unconditionally 2 none sz [m] skip if data memory is zero 1 note none sza [m] skip if data memory is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memory is zero 1 note none snz [m].i skip if bit i of data memory is not zero 1 note none siz [m] skip if increment data memory is zero 1 note none sdz [m] skip if decrement data memory is zero 1 note none siza [m] skip if increment data memory is zero with result in acc 1 note none sdza [m] skip if decrement data memory is zero with result in acc 1 note none call addr subroutine call 2 none ret return from subroutine 2 none ret a,x return from subroutine and load immediate data to acc 2 none reti return from interrupt 2 none table read operation tabrd [m] read table (specifc page) to tblh and data memory 2 note none tabrdc [m] read table (current page) to tblh and data memory 2 note none tabrdl [m] read table (last page) to tblh and data memory 2 note none miscellaneous nop no operation 1 none clr [m] clear data memory 1 note none set [m] set data memory 1 note none clr wdt clear watchdog timer 1 to, pdf clr wdt1 pre-clear watchdog timer 1 to, pdf clr wdt2 pre-clear watchdog timer 1 to, pdf swap [m] swap nibbles of data memory 1 note none swapa [m] swap nibbles of data memory with result in acc 1 none halt enter power down mode 1 to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the t o and pdf flags may be af fected by the execution sta tus. t he t o a nd pdf fl ags a re c leared a fter bot h clr w dt1 a nd clr w dt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.41 116 april 11, 2017 rev. 1.41 117 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.41 118 april 11, 2017 rev. 1.41 119 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.41 118 april 11, 2017 rev. 1.41 119 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.41 120 april 11, 2017 rev. 1.41 121 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.41 120 april 11, 2017 rev. 1.41 121 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.41 122 april 11, 2017 rev. 1.41 123 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.41 122 april 11, 2017 rev. 1.41 123 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.41 124 april 11, 2017 rev. 1.41 125 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.41 124 april 11, 2017 rev. 1.41 125 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.41 126 april 11, 2017 rev. 1.41 127 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product t ape and reel specifcations) ? packing meterials information ? carton information
rev. 1.41 126 april 11, 2017 rev. 1.41 127 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom 8-pin dip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.355 0.365 0.400 b 0.240 0.250 0.280 c 0.115 0.130 0.195 d 0.115 0.130 0.150 e 0.014 0.018 0.022 f 0.045 0.060 0.070 g 0.100 bsc h 0.300 0.310 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 9.02 9.27 10.16 b 6.10 6.35 7.11 c 2.92 3.30 4.95 d 2.92 3.30 3.81 e 0.36 0.46 0.56 f 1.14 1.52 1.78 g 2.54 bsc h 7.26 7.87 8.26 i 10.92
rev. 1.41 128 april 11, 2017 rev. 1.41 129 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom 8-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c 0.193 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a f 6.00 bsc b 3.90 bsc c 0.31 0.51 c 4.90 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.41 128 april 11, 2017 rev. 1.41 129 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom 10-pin msop outline dimensions symbol dimensions in inch min. nom. max. a 0.043 a1 0.000 0.006 a2 0.030 0.033 0.037 b 0.007 0.013 c 0.003 0.009 d 0.118 bsc e 0.193 bsc e1 0.118 bsc e 0.020 bsc l 0.016 0.024 0.031 l1 0.037 bsc y 0.004 0 8 symbol dimensions in mm min. nom. max. a 1.10 a1 0.00 0.15 a2 0.75 0.85 0.95 b 0.17 0.33 c 0.08 0.23 d 3.00 bsc e 4.90 bsc e1 3.00 bsc e 0.50 bsc l 0.40 0.60 0.80 l1 0.95 bsc y 0.10 0 8
rev. 1.41 130 april 11, 2017 rev. 1.41 131 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom 16-pin nsop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c' 0.390 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 D 8 symbol dimensions in mm min. nom. max. a 6 bsc b 3.9 bsc c 0.31 0.51 c' 9.9 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 D 8
rev. 1.41 130 april 11, 2017 rev. 1.41 131 april 11, 2017 HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom HT66F007/ht66f008 cost-effective a/d flash mcu with eeprom copyright ? 2017 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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